Search - fpga ram

[Communication-Mobile] irig

Description: irig-b 单片机解析 MSP430系列单片机是集成度高、超低功耗的16位单片机。Cyclone系列芯片是Altera公司推出的低价格、RAM可达288 kb的高容量的FPGA。IRIG-B码广泛应用于靶场时间信息的传递和各系统的时间同步。详细介绍了IRIG-B码解码电路和调制电路的硬件设计。MSP430的软件采用C语言编写，使程序有很强的可移植性。-irig-b microcontroller MSP430 Microcontroller analysis are highly integrated, ultra-low-power 16-bit microcontroller. Altera' s Cyclone series of chips are launched in low-cost, RAM up to 288 kb of high-capacity FPGA. IRIG-B time code range is widely used in the transmission of messages and the system time synchronization. Details of the IRIG-B decoding circuit and modulation circuit of the hardware design. MSP430 software using C language, so that programs are highly portable.
Platform: | Size: 11264 | Author: JEFF | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[assembly language] fifo_ram

Description: 同步fifo，基于FPGA的VHDL编程，已调试。-fifo-ram
Platform: | Size: 1024 | Author: 曾馨月 | Hits:

[Windows Develop] read

Description: 在FPGA内部实现RAM块中数据的读出，简单方便。-Internal implementation in FPGA block RAM read data
Platform: | Size: 582656 | Author: 庞利会 | Hits:

[Embeded-SCM Develop] ramtest

Description: 用verilog语言往内部FPGA的sram中读写数据，即把1—4写入ram的1—4的地址里-Verilog language within the FPGA with the sram to read and write data, that is 1-4, 1-4 to write the address in ram
Platform: | Size: 58368 | Author: 蓝冰 | Hits:

[VHDL-FPGA-Verilog] chunchuqidesheji

Description: 在计算机系统中，一般都提供一定数量的存储器。在用FPGA实现的系统中，除可以使用FPGA本身提供的存储器资源外，还可以使用FPGA的外部扩充存储器。本实验要求设计一个32×8 RAM，如下图所示，它包含5位地址、8位数据口和一个写控制端口。-In the computer system, generally provide a certain amount of memory. FPGA implementation of the system in use, unless you can use the FPGA itself memory resources, you can also use the FPGA' s external expansion memory. In this study, to design a 32 × 8 RAM, as shown below, which contains five addresses, 8-bit data port and a write control port.
Platform: | Size: 903168 | Author: shenlina | Hits:

[VHDL-FPGA-Verilog] 256fft

Description:
Platform: | Size: 209920 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA

Description: 在 Spartan-3 系列 FPGA 中将查找表用作分布式 RAM-using_the_LUT_as_distributed_RAM_in_Spartan-3_FPGA
Platform: | Size: 7168 | Author: lishiwei | Hits:

[VHDL-FPGA-Verilog] m_decoder

Description: 恢复以曼彻斯特编码格式输入的mdi信号成实际数据并存储在双端口RAM后以中断方式通知DSP读取数据，所需双端口RAM程序可以从相应的FPGA编译系统中产生-A return to the Manchester encoded signal is input into the actual data mdi and stored in the dual-port RAM notify the DSP after the break to read the data, the required dual-port RAM from the corresponding FPGA program can be generated build system
Platform: | Size: 2048 | Author: 周宽裕 | Hits:

[VHDL-FPGA-Verilog] m_encoder

Description: 将写入的数据用曼彻斯特码格式从meout口输出，所需内部存储单元可根据所使用不同的FPGA类型由相应的编译软件产生所需双端口RAM模块-The data will be written by Manchester code format from meout port output, the required internal storage unit can be used according to the different types of FPGA Compiler software from the corresponding dual-port RAM module to generate the required
Platform: | Size: 2048 | Author: 周宽裕 | Hits:

[VHDL-FPGA-Verilog] vlsiram

Description: VHDL RAM 16 * 8 source code FPGA
Platform: | Size: 1024 | Author: kirtikumar | Hits:

[matlab] MATLAB_HexToMif

Description: 将Hex格式的数据转成Mif格式，供FPGA搭建系统时初始化RAM.-Hex format data will be converted into Mif format for initialization when the FPGA set up the system RAM.
Platform: | Size: 1024 | Author: 杨军 | Hits:

[VHDL-FPGA-Verilog] rea_wri_ram

Description: 用FPGA实现对RAM的读写，实现特定的功能-FPGA implementation of the RAM with read and write, to achieve a specific function
Platform: | Size: 2048 | Author: 孙倩华 | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] synth_fft

Description: 甘地大学电子专业Ray Ranjan Varghese设计的FPGA实现FFT，采用的是单精度的浮点，采用IEEE745格式的浮点+ROM RAM的方式成功实现FFT，含有设计报告和设计源代码，并有测试文件，真的很不错。 -Gandhi University of Electronic Design Professional Ray Ranjan Varghese FPGA realization of FFT, using a single precision floating-point, using IEEE745 floating-point+ ROM RAM format, the successful implementation of the FFT, design reports and design with source code, and test file Really good.
Platform: | Size: 418816 | Author: 何渊泽 | Hits:

[Other Embeded program] The-pulse-signal-generator

Description: 脉冲信号发生器：采用DDS技术实现脉冲信号的周期、脉冲宽度、幅值的数控调节。通过单片机与FPGA的并行通信技术将频率控制字及矩形脉冲数据传送给FPGA的双口RAM。模拟输出通道则将信号通过100MHz、8位D/A转换器将波形数据转换成模拟脉冲信号，最后通过高速运放构成的放大器放大，实现幅度连续可调。-The pulse signal generator: using the DDS technology to achieve the pulse signal cycles, pulse width and amplitude of the numerical control regulation. Through the microcontroller and FPGA parallel communications will frequency control characters and rectangular pulse data to the FPGA double mouth RAM. Analog output channel will signal through 100MHz, eight D/A converter will waveforms converted into analog pulse signal, finally through high-speed op-amp constitute the amplifier amplification, realize the continuous adjustable range.
Platform: | Size: 19456 | Author: 张节 | Hits:

[VHDL-FPGA-Verilog] RAMaddressGenerator

Description: 基于FPGA（EP2C5T144开发板）的RAM的地址发生器，初学者适用-Based on FPGA (EP2C5T144 development board) RAM address generator for beginners
Platform: | Size: 266240 | Author: 周奕 | Hits:

[SCM] RAM_test

Description: ADSPTS201相关程序，总线方式、DMA方式读写片外SDRM和FPGA内部RAM数据 -ADSPTS201 procedures, the bus mode, DMA mode and the FPGA to read and write chip internal RAM data SDRM
Platform: | Size: 1024 | Author: litao | Hits:

[VHDL-FPGA-Verilog] DoubleRAM

Description: actel fpga kit 双端口RAM 实验-actel fpga kit dual-port RAM test
Platform: | Size: 614400 | Author: zhouwj | Hits:

[VHDL-FPGA-Verilog] DDR_FLASH_VHDL_Verilog

Description: FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
Platform: | Size: 17408 | Author: rickdecent | Hits:

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